1. Field of the Invention
The present invention pertains to the field of electrostatic and mechanical chucks for semiconductor process chambers. More particularly, the present invention pertains to an apparatus, technology and method(s) for increasing temperature uniformity of workpieces, such as semiconductor wafers, during processing steps, such as plasma etching steps.
2. Description of the Related Art
The processing of semiconductor wafers in process chambers may require that the wafer be supported by a pedestal, which is commonly known as a chuck. Chucks may be either mechanical or electrostatic. Mechanical chucks include one or more clamps to secure the wafer to a support. Electrostatic chucks rely on the electrostatic pressure generated by an electrode energized by a DC voltage source to secure the wafer to the chuck.
Different processing steps typically require different processing temperatures. One commonly used method of varying the wafer temperature is by varying the temperature of the wafer backside, the side of the wafer in contact with the mechanical or electrostatic chuck. An inert gas or a combination of inert gases, such as helium, nitrogen or argon, for example, is often used to regulate the backside temperature of the wafer. This inert gas is directed toward the wafer backside at a predetermined temperature and pressure. When electrostatic chucks are used, however, it has been found that at a given inert gas pressure, the temperature of the wafer may be different toward the center than toward the peripheral area of the wafer. For example, the temperature toward the center of the wafer may be lower than the temperature toward the peripheral edge of the wafer, for a given inert gas pressure. This temperature differential between central and peripheral areas of the wafer is generally undesirable, as it may directly and adversely affect the effectiveness of the processing steps during the formation of the integrated circuits on the wafer.
Highly selective etch processes, for example, require a high degree of selectivity uniformity. Selectivity uniformity, in terms of highly selective etch process technology, refers to the ability of an etch step to etch only that portion of the device (e.g., transistor) necessary to form the desired structure (such as a trench), and to do so in a uniform manner for all such devices across the width of the wafer. Selectivity uniformity may also be defined as the selectivity across the wafer (maximum delta number) divided by the average selectivity. For example, it may be desired to etch a trench between adjacent 1T transistors, which trench is to be filed with a conductive (tungsten, for example) plug to form an electrical interconnect with the underlying substrate. If there is poor selectivity uniformity, a same etch step may produce different results near the center of the wafer than it does near the periphery of the wafer. For example, if the temperature at or near the edge of the wafer is greater than the temperature at or near the periphery of the wafer (or if the magnitude of the temperature differential between the center and the periphery of the wafer is impermissibly large), a same etch step may provide good corner protection near the periphery and poor corner protection near the center of the wafer. Indeed, such an etch step may properly etch the layer between the gate structures (e.g. PSG or BPSG, for example) without etching the layer (e.g. silicon nitride, for example) covering the underlying gate (e.g. a polysilicon gate layer, for example) structure near the periphery while unacceptably etching a portion of the silicon nitride near the center of the device, a phenomena sometimes called xe2x80x9cpunch throughxe2x80x9d. xe2x80x9cPunch throughxe2x80x9d can damage the underlying gate structure and thus adversely affect both product quality of the resultant devices and the yield of the process.
It is thus desirable to control the temperature of the wafer so as to improve the temperature uniformity across the width of the wafer. Moreover, it is desirable to improve the selectivity uniformity of etch steps in semiconductor process chambers. Attempts to address the issue of temperature uniformity across the width of silicon wafers have thus far centered upon a complex system of seals, chuck topographic features and/or multiple supplies of coolant gasses at varying temperatures and pressures. However, such systems may require complete redesigns of existing process chambers and/or gas supply mechanisms. Such re-designs may, in many situations, prove to be prohibitively costly. Indeed, as the marketplace for semiconductors sometimes resembles a commodity market, such costly re-designs may negatively affect the semiconductor manufacturer""s ability to bring competitively-priced products to market, notwithstanding any marginal increase in yield such systems may provide.
An object of the present invention, therefore, is to provide improved temperature uniformity across the width of workpieces (such as, for example, silicon wafers) held by an electrostatic or mechanical chuck. Another object of the present invention is to improve the selectivity uniformity of etch steps in semiconductor process chambers. It is a further object of the invention to provide an electrostatic or a mechanical chuck assembly that exhibits improved temperature uniformity characteristics and that does not require extensive and/or costly modifications to existing processing chambers and/or gas supply mechanisms.
In accordance with the above-described objects and those that will be mentioned and will become apparent below, an electrostatic chuck assembly, according to an embodiment of the present invention, comprises:
a first dielectric layer including a first and a second surface;
a first electrode in contact with the first surface;
at least one gas conduit;
a second electrode in contact with the second surface, the second electrode including:
a circumference defined by a first radius,
a central region; and
an annular peripheral region concentric with the central region and bounded by the circumference and an inner boundary defined by a second radius, the second radius being no less than about 60% of the first radius. A plurality of gas inlets are defined only in the peripheral region, each of the plurality of gas inlets being in fluid communication with the at least one gas conduit.
According to further embodiments, a second dielectric layer may be disposed on the second electrode in such a manner as to allow free passage of gas through each of the plurality of gas inlets. The second dielectric layer may include a polyimide and/or a ceramic material. The surface of at least the central region is preferably sufficiently irregular to allow diffusion of gas from the peripheral region to within the central region when a workpiece is disposed on the chuck.
The present invention may also be viewed as a method for cooling a workpiece in a processing chamber, comprising the steps of:
supporting the workpiece on a substantially planar surface, the surface having a first radius defining a circumference thereof, a central region and an annular peripheral region concentric with the central region and bounded by the circumference and a second radius, the second radius being no less than about 60% of the first radius, the peripheral region only defining a plurality of gas inlets; and
delivering gas directly only to the peripheral region, through at least one gas conduit in fluid communication with the plurality of gas inlets.
According to further embodiments, the delivering step may deliver the gas or gasses at a pressure effective to cool both the central and peripheral regions of the workpiece to within a temperature differential consistent with further processing of the workpiece. The temperature differential may be less than about 15xc2x0 C. The delivering step may deliver the gas or gasses at a pressure effective to cause diffusion of gas from the plurality of gas inlets to the central region, via one or more interstitial spaces between the substantially planar surface and the workpiece supported thereby. The substantially planar surface may be a top-most surface of an electrostatic chuck, in which case the top-most surface may be adapted to contact a backside of a semiconductor wafer held by the electrostatic chuck. The substantially planar surface may be a top-most surface of a mechanical chuck, in which case the top-most surface may be adapted to contact a backside of a semiconductor wafer held by the mechanical chuck.
The present invention, according to a still further embodiment, may be viewed as an apparatus for processing a semiconductor wafer, comprising:
a process chamber;
an RF source;
a gas introduction port for introducing a process gas into the process chamber;
a gas evacuation port for evacuating the process gas from the process chamber;
a chuck assembly for holding and supporting the semiconductor wafer within the process chamber, the chuck assembly including:
a first dielectric layer including a first and a second surface;
a first electrode in contact with the first surface;
at least one gas conduit;
a second electrode in contact with the second surface, the second electrode including:
a circumference defined by a first radius,
a central region; and
an annular peripheral region concentric with the central region and bounded by the circumference and an inner boundary defined by a second radius, the second radius being no less than about 60% of the first radius. A plurality of gas inlets are preferably defined only in the peripheral region, each of the plurality of gas inlets being in fluid communication with the at least one gas conduit.
A second dielectric layer may be disposed on the second electrode in such a manner as to allow free passage of gas through each of the plurality of gas inlets. The second dielectric layer may include polyimide and/or a ceramic material. The surface of at least the central region is preferably sufficiently irregular to allow diffusion of gas from the peripheral region to within the central region when a workpiece is disposed on the chuck.
The foregoing and other features of the invention are described in detail below and set forth in the appended claims.